SRAM is a type of random access memory wherein each data bit is stored on the transistors of two cross-coupled inverters. The bit cell has two stable states corresponding to a logic “1” or “0”. Two additional access transistors or pass transistors may be used for controlling the access to the storage cell during read and write operations. The access transistors may be connected to the storage cell at a respective storage node. The storage nodes are complementary nodes, and a logic “1” may hence be represented by a high voltage at a first storage node and a low voltage at a second storage node. Accordingly, a logic “0” may be represented by a low voltage at the first storage node and a high voltage at the second storage node. Data may be written to the storage cell by a word line for opening the access transistors and transferring a charge from complementary bit lines to the respective storage nodes. Data may be read from the storage cell by opening the access transistors and sensing the voltage via the bit lines.
As these kinds of memory cells are volatile to their nature, it has been proposed to use programmable resistive elements, such as magnetic tunnel junctions (MTJs), to provide non-volatile data storage. The programmed resistive state is maintained even when a supply voltage of the storage cell is disconnected, and therefore data may be stored by such elements in a non-volatile fashion.
Even though such techniques have been proposed, the general trend of miniaturisation causes a continuous strive for faster and more energy efficient memory cells having a reduced area.